TCC6060: rsync backup report for file projects.dirlist
Time: 2009-Dec-16 02:40:47 Wed
------------------------------- backup v3.14 2009-08-01 --------
TCC6060 "rsync" backup log for file "projects.dirlist"
Email sent to: john@larsen-family.us,jlarsen@tccsecure.com
Number of days backups kept: 100 (0: Keep all)
Script started at: 2009-Dec-16 02:01:12 Wed
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Starting uptime, load average, and users:
02:01:12 up 1 day, 16:23, 0 users, load average: 0.00, 0.00, 0.00
USER TTY LOGIN@ IDLE JCPU PCPU WHAT
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Starting disk usage:
Filesystem Size Used Avail Use% Mounted on
//cipher/development projects/Projects-Product Development-Improvement
274G 246G 28G 90% /projects
//cipher/development projects
274G 246G 28G 90% /mnt/cipher/projects
//cipher/documentation
196G 174G 23G 89% /mnt/cipher/documentation
//Domino/tccwork4 14G 12G 2.1G 85% /mnt/domino/tccwork4
//Domino/tccwork5 9.9G 3.2G 6.7G 33% /mnt/domino/tccwork5
//Domino/swdev6 19G 12G 6.6G 64% /mnt/domino/swdev6
//Domino/swdev7 18G 14G 3.3G 82% /mnt/domino/swdev7
//cipher/larsen 49G 28G 22G 56% /mnt/cipher/larsen
//cipher/tools 196G 174G 23G 89% /mnt/cipher/tools
C:/cygwin/bin 72G 31G 42G 43% /usr/bin
C:/cygwin/lib 72G 31G 42G 43% /usr/lib
//Domino/home 11G 9.7G 533M 95% /mnt/domino/home
//Domino/view 14G 7.3G 6.6G 53% /mnt/domino/view
//cipher/mac 196G 174G 23G 89% /mnt/cipher/mac
C:/cygwin 72G 31G 42G 43% /
C:/home 72G 31G 42G 43% /home
C:/mnt 72G 31G 42G 43% /mnt
C: 72G 31G 42G 43% /c
D: 932G 533G 400G 58% /d
M: 79G 30G 49G 38% /m
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rsync backup started at: 2009-Dec-16 02:01:15 Wed
Source directory: /projects
Destination directory: /mnt/cipher/projects/backups/projects/projects
rsync options: -rltDuvzR --rsync-path="/usr/bin/rsync" --filter='exclude Temporary Internet Files' --filter='exclude Application Data' --filter='exclude Application Data' --filter='exclude Cookies' --filter='exclude previous_data.*' --filter='exclude /c/home/larsen/ping_test/*.png' --filter='exclude /c/home/larsen/junk/png' --delete --timeout=120 --backup --backup-dir="/mnt/cipher/projects/backups/projects.091216-0201"
sending incremental file list
/projects/
/projects/backup.rsync
/projects/JN7236 72B Product Development Project/9-In Progress/CompSpecSheets/IRs/
/projects/JN7236 72B Product Development Project/9-In Progress/CompSpecSheets/IRs/421-25734_Rev2_vs_rev8_lst.txt
/projects/JN7236 72B Product Development Project/9-In Progress/CompSpecSheets/IRs/09097/
/projects/JN7236 72B Product Development Project/9-In Progress/CompSpecSheets/IRs/09097/424-25734_PCB Design Checklist.DOC
/projects/JN7236 72B Product Development Project/9-In Progress/CompSpecSheets/IRs/09097/~$4-25734_PCB Design Checklist.DOC
/projects/PD7155 Model 70-4-Product Development Project/5-Phase II Development/2.1-Hardware Specifications/Figures/
/projects/PD7155 Model 70-4-Product Development Project/5-Phase II Development/2.1-Hardware Specifications/Figures/Model70_BLTF_CPU_Board_Slot_New.vsd
/projects/PD7155 Model 70-4-Product Development Project/5-Phase II Development/2.1-Hardware Specifications/Figures/Model70_BLTF_InterfaceBoard_Slot_New.vsd
/projects/PD7155 Model 70-4-Product Development Project/5-Phase II Development/2.1-Hardware Specifications/In_Process/
/projects/PD7155 Model 70-4-Product Development Project/5-Phase II Development/2.1-Hardware Specifications/In_Process/553-25591_Model70_ATE_HardwareDesignSpec_Rev9.doc
/projects/PD7155 Model 70-4-Product Development Project/5-Phase II Development/2.4-Design Checklist/424-25591_CarrierBoard_Right/
/projects/PD7155 Model 70-4-Product Development Project/9-In Progress/WeeklyMeetings/
/projects/PD7155 Model 70-4-Product Development Project/9-In Progress/WeeklyMeetings/MODEL70-4_BLTF_BOM_DWG_STATUS.xls
/projects/PD7320 72A-TI Product Development Project/3-Phase I Concept/6.0-Functional Requirements Specification/
/projects/PD7320 72A-TI Product Development Project/3-Phase I Concept/6.0-Functional Requirements Specification/~$nctional Specification E2 E1 and D1 DSD 72A-TI rev 50.doc
/projects/PD7320 72A-TI Product Development Project/5-Phase II Development/3-Test Plans/1-Test Plan(s)/
/projects/PD7320 72A-TI Product Development Project/5-Phase II Development/3-Test Plans/1-Test Plan(s)/72A-TI HW Test Plan_in_process.DOC
/projects/PD7320 72A-TI Product Development Project/5-Phase II Development/3-Test Plans/1-Test Plan(s)/~$A-TI HW Test Plan_in_process.DOC
/projects/PD7320 72A-TI Product Development Project/9-In Progress/DVT_Testing/Scope_Images/
/projects/PD7320 72A-TI Product Development Project/9-In Progress/DVT_Testing/Scope_Images/PowerOn_5V_3p3V_Softstart.TIF
/projects/PD7320 72A-TI Product Development Project/9-In Progress/ECA/ECA09088_Cable_Ver8/Drawings/
/projects/PD7320 72A-TI Product Development Project/9-In Progress/MUX_Sync_Special/CPLD/
/projects/PD7320 72A-TI Product Development Project/9-In Progress/MUX_Sync_Special/CPLD/Mux_Sync_CPLD.qws
/projects/PD7320 72A-TI Product Development Project/9-In Progress/MUX_Sync_Special/CPLD/Mux_Sync_CPLD.vhd
/projects/PD7320 72A-TI Product Development Project/9-In Progress/MUX_Sync_Special/CPLD/Mux_Sync_CPLD.vhd.bak
/projects/PD7320 72A-TI Product Development Project/9-In Progress/MUX_Sync_Special/CPLD/db/
deleting projects/PD7320 72A-TI Product Development Project/9-In Progress/MUX_Sync_Special/CPLD/db/Mux_Sync_CPLD.tmw_info
/projects/PD7320 72A-TI Product Development Project/9-In Progress/MUX_Sync_Special/CPLD/db/Mux_Sync_CPLD.eco.cdb
/projects/PD7320 72A-TI Product Development Project/9-In Progress/MUX_Sync_Special/CPLD/db/Mux_Sync_CPLD.sld_design_entry.sci
/projects/PD7320 72A-TI Product Development Project/9-In Progress/PCB_Layout/latest files from PCB design house/
deleting projects/PD7320 72A-TI Product Development Project/9-In Progress/PCB_Layout/latest files from PCB design house/~$424-25680-R50_ARC.pcb.inf
/projects/Special Projects/ATI Integration December 2009/
/projects/Time Tracking/
/projects/Time Tracking/Hours Reporting Cardone.xls
/projects/Time Tracking/Hours Reporting Dias.xls
/projects/Time Tracking/Hours Reporting Dubois.xls
/projects/Time Tracking/Hours Reporting Hureau.xls
/projects/Time Tracking/Hours Reporting Krieger.xls
/projects/Time Tracking/Hours Reporting Larsen.xls
/projects/Time Tracking/Hours Reporting Madden.xls
/projects/Time Tracking/Hours Reporting Maher.xls
/projects/Time Tracking/Hours Reporting Matern(working).xls
/projects/Time Tracking/Hours Reporting Nivens(working).xls
/projects/Time Tracking/Hours Reporting Peterson.xls
/projects/Time Tracking/Hours Reporting Rickless.xls
/projects/Time Tracking/Hours Reporting Thompson.xls
sent 20194966 bytes received 3507 bytes 13398.66 bytes/sec
total size is 17954782876 speedup is 888.92
rsync backup ended at: 2009-Dec-16 02:26:23 Wed
cp: cannot create regular file `/mnt/cipher/projects/backups/projects.091216-0201/backup_log.txt': No such file or directory
----------------------------------------------------------------
rsync backup started at: 2009-Dec-16 02:26:55 Wed
Source directory: /projects
Destination directory: /d/cipher/projects
rsync options: -rltDuvzR --rsync-path="/usr/bin/rsync" --filter='exclude Temporary Internet Files' --filter='exclude Application Data' --filter='exclude Application Data' --filter='exclude Cookies' --filter='exclude previous_data.*' --filter='exclude /c/home/larsen/ping_test/*.png' --filter='exclude /c/home/larsen/junk/png' --delete --timeout=120 --backup --backup-dir="/d/cipher.091216-0201"
sending incremental file list
/projects/
/projects/backup.rsync
/projects/JN7236 72B Product Development Project/9-In Progress/CompSpecSheets/IRs/
/projects/JN7236 72B Product Development Project/9-In Progress/CompSpecSheets/IRs/421-25734_Rev2_vs_rev8_lst.txt
/projects/JN7236 72B Product Development Project/9-In Progress/CompSpecSheets/IRs/09097/
/projects/JN7236 72B Product Development Project/9-In Progress/CompSpecSheets/IRs/09097/424-25734_PCB Design Checklist.DOC
/projects/JN7236 72B Product Development Project/9-In Progress/CompSpecSheets/IRs/09097/~$4-25734_PCB Design Checklist.DOC
/projects/PD7155 Model 70-4-Product Development Project/5-Phase II Development/2.1-Hardware Specifications/Figures/
/projects/PD7155 Model 70-4-Product Development Project/5-Phase II Development/2.1-Hardware Specifications/Figures/Model70_BLTF_CPU_Board_Slot_New.vsd
/projects/PD7155 Model 70-4-Product Development Project/5-Phase II Development/2.1-Hardware Specifications/Figures/Model70_BLTF_InterfaceBoard_Slot_New.vsd
/projects/PD7155 Model 70-4-Product Development Project/5-Phase II Development/2.1-Hardware Specifications/In_Process/
/projects/PD7155 Model 70-4-Product Development Project/5-Phase II Development/2.1-Hardware Specifications/In_Process/553-25591_Model70_ATE_HardwareDesignSpec_Rev9.doc
/projects/PD7155 Model 70-4-Product Development Project/5-Phase II Development/2.4-Design Checklist/424-25591_CarrierBoard_Right/
/projects/PD7155 Model 70-4-Product Development Project/9-In Progress/WeeklyMeetings/
/projects/PD7155 Model 70-4-Product Development Project/9-In Progress/WeeklyMeetings/MODEL70-4_BLTF_BOM_DWG_STATUS.xls
/projects/PD7320 72A-TI Product Development Project/3-Phase I Concept/6.0-Functional Requirements Specification/
/projects/PD7320 72A-TI Product Development Project/3-Phase I Concept/6.0-Functional Requirements Specification/~$nctional Specification E2 E1 and D1 DSD 72A-TI rev 50.doc
/projects/PD7320 72A-TI Product Development Project/5-Phase II Development/3-Test Plans/1-Test Plan(s)/
/projects/PD7320 72A-TI Product Development Project/5-Phase II Development/3-Test Plans/1-Test Plan(s)/72A-TI HW Test Plan_in_process.DOC
/projects/PD7320 72A-TI Product Development Project/5-Phase II Development/3-Test Plans/1-Test Plan(s)/~$A-TI HW Test Plan_in_process.DOC
/projects/PD7320 72A-TI Product Development Project/9-In Progress/DVT_Testing/Scope_Images/
/projects/PD7320 72A-TI Product Development Project/9-In Progress/DVT_Testing/Scope_Images/PowerOn_5V_3p3V_Softstart.TIF
/projects/PD7320 72A-TI Product Development Project/9-In Progress/ECA/ECA09088_Cable_Ver8/Drawings/
/projects/PD7320 72A-TI Product Development Project/9-In Progress/MUX_Sync_Special/CPLD/
/projects/PD7320 72A-TI Product Development Project/9-In Progress/MUX_Sync_Special/CPLD/Mux_Sync_CPLD.qws
/projects/PD7320 72A-TI Product Development Project/9-In Progress/MUX_Sync_Special/CPLD/Mux_Sync_CPLD.vhd
/projects/PD7320 72A-TI Product Development Project/9-In Progress/MUX_Sync_Special/CPLD/Mux_Sync_CPLD.vhd.bak
/projects/PD7320 72A-TI Product Development Project/9-In Progress/MUX_Sync_Special/CPLD/db/
deleting projects/PD7320 72A-TI Product Development Project/9-In Progress/MUX_Sync_Special/CPLD/db/Mux_Sync_CPLD.tmw_info
/projects/PD7320 72A-TI Product Development Project/9-In Progress/MUX_Sync_Special/CPLD/db/Mux_Sync_CPLD.eco.cdb
/projects/PD7320 72A-TI Product Development Project/9-In Progress/MUX_Sync_Special/CPLD/db/Mux_Sync_CPLD.sld_design_entry.sci
/projects/PD7320 72A-TI Product Development Project/9-In Progress/PCB_Layout/latest files from PCB design house/
deleting projects/PD7320 72A-TI Product Development Project/9-In Progress/PCB_Layout/latest files from PCB design house/~$424-25680-R50_ARC.pcb.inf
/projects/Special Projects/ATI Integration December 2009/
/projects/Time Tracking/
/projects/Time Tracking/Hours Reporting Cardone.xls
/projects/Time Tracking/Hours Reporting Dias.xls
/projects/Time Tracking/Hours Reporting Dubois.xls
/projects/Time Tracking/Hours Reporting Hureau.xls
/projects/Time Tracking/Hours Reporting Krieger.xls
/projects/Time Tracking/Hours Reporting Larsen.xls
/projects/Time Tracking/Hours Reporting Madden.xls
/projects/Time Tracking/Hours Reporting Maher.xls
/projects/Time Tracking/Hours Reporting Matern(working).xls
/projects/Time Tracking/Hours Reporting Nivens(working).xls
/projects/Time Tracking/Hours Reporting Peterson.xls
/projects/Time Tracking/Hours Reporting Rickless.xls
/projects/Time Tracking/Hours Reporting Thompson.xls
sent 20194966 bytes received 3507 bytes 24468.17 bytes/sec
total size is 17954782876 speedup is 888.92
rsync backup ended at: 2009-Dec-16 02:40:40 Wed
----------------------------------------------------------------
Ending uptime, load average, and users:
02:40:45 up 1 day, 17:02, 0 users, load average: 0.00, 0.00, 0.00
USER TTY LOGIN@ IDLE JCPU PCPU WHAT
----------------------------------------------------------------
Ending disk usage:
Filesystem Size Used Avail Use% Mounted on
//cipher/development projects/Projects-Product Development-Improvement
274G 246G 28G 90% /projects
//cipher/development projects
274G 246G 28G 90% /mnt/cipher/projects
//cipher/documentation
196G 174G 23G 89% /mnt/cipher/documentation
//Domino/tccwork4 14G 12G 2.1G 85% /mnt/domino/tccwork4
//Domino/tccwork5 9.9G 3.2G 6.7G 33% /mnt/domino/tccwork5
//Domino/swdev6 19G 12G 6.6G 64% /mnt/domino/swdev6
//Domino/swdev7 18G 14G 3.3G 82% /mnt/domino/swdev7
//cipher/larsen 49G 28G 22G 56% /mnt/cipher/larsen
//cipher/tools 196G 174G 23G 89% /mnt/cipher/tools
C:/cygwin/bin 72G 31G 42G 43% /usr/bin
C:/cygwin/lib 72G 31G 42G 43% /usr/lib
//Domino/home 11G 9.7G 531M 95% /mnt/domino/home
//Domino/view 14G 7.3G 6.6G 53% /mnt/domino/view
//cipher/mac 196G 174G 23G 89% /mnt/cipher/mac
C:/cygwin 72G 31G 42G 43% /
C:/home 72G 31G 42G 43% /home
C:/mnt 72G 31G 42G 43% /mnt
C: 72G 31G 42G 43% /c
D: 932G 533G 400G 58% /d
M: 79G 30G 49G 38% /m
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Script ended at: 2009-Dec-16 02:40:46 Wed
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